The present invention relates to a series-parallel A/D (Analog-to-Digital) converter and, in particular, to a reference voltage generating circuit for use in a series-parallel A/D converter.
A/D converters are classified into parallel type and series-parallel type.
A parallel A/D converter has 2.sup.n comparators and 2.sup.n reference resistors, where n is resolution and presented by a number of bits. The 2.sup.n reference resistors divide the full-scale voltage into various voltages. The comparators compare the voltages thus obtained with an input voltage (i.e., input analog data), thereby converting the input analog data to digital data. The parallel A/D converter generally achieves high-speed, high-precision analog-to-digital conversion. However, the higher its resolution, the more elements it needs to have, and the more power it consumes.
A series-parallel A/D converter converts input analog data in two steps. In the first step it converts the first half of the data to upper bits. In the second step it converts the second half of the data to lower bits. The reference voltages are determined by the result of comparison performed by the comparators used to convert the second half of the data to lower bits. The series-parallel A/D converter can be composed of far less elements than a parallel A/D converter; it is smaller and consumes less power, than a parallel A/D converter. However, it is inferior to a parallel A/D converter in terms of operating speed and conversion precision.
FIG. 1 shows a 6-bit, 2-step series-parallel A/D converter. For simplicity, it is assumed that this A/D converter is designed to convert analog data (i.e., input voltage) Vin into 6-bit digital data, by first converting the first half of the input data to three bits and then converting the second half of the input data to three bits.
As shown in FIG. 1, the series-parallel A/D converter comprises a reference voltage generator 1, two comparator sections 2 and 4, two encoders 3 and 5, and digital correction circuit 6.
The reference voltage generator 1 has 64 (=2.sup.6) reference resistors R0 to R63. The resistors R0 to R63 have the same resistance and divide a full-scale voltage (VRT-VRB) into different voltages, any adjacent two of which differ by the same value. The resistors R0 to R62 are connected in series, forming a line. This line is folded back repeatedly, in the form of a rectangular wave, each longer straight segment consisting of four resistors. As a result, the reference resistors R0 to R63 are arranged in 16 rows and 4 columns.
The reference resistors R0 to R63 form 8 (=2.sup.3) blocks BL0 to BL7, each consisting of two rows of resistors, or eight reference resistors. To be more specific, the block BL0 is composed of the resistors R0 to R7; the resistor R0 is connected to a terminal 11, and the resistor R7 to the comparator CPM0 of the first comparator section 2. The block BL1 is composed of the resistors R8 to R15; the resistors R8 and R15 are connected to the comparators CPM0 and CPM1 of the first comparator section 2, respectively. The block BL7 is composed of the resistors R56 to R63; the resistor R56 is connected to the comparator CPM6, and the resistor R63 to a terminal 12.
The first comparator section 2 is provided to process the first half of the input analog data Vin, thereby to generate upper three bits of digital data. The second comparator section 4 is used to process the second half of the input analog data Vin, thereby to generate lower three bits of digital data.
The ends of each block and the nodes among the eight resistors thereof are connected to the comparators CPL0 to CPL8 of the second comparator section 4. The reference voltages applied to the comparators CPL0 to CPL8 are generated in one of the blocks BL0 to BL7 which has been selected.
When any block BLi is selected, where i is an integer ranging from 0 to 7, one of the reference voltages generated in the block BLi overlaps one of the reference voltages generated in the next block BLi+1. The overlap is provided to cancel out the difference between the result of comparison performed by the first comparator section 2 and the result of comparison performed by the second comparator section 4.
The switches included in each block of resistors are simultaneously turned on or off. More precisely, one of the blocks BL0 to BL7 is selected in accordance with the result of the comparison performed by the first comparator section 2, and all switches of a block thus selected are turned on, while all switches of any other block are turned off. When the switches of the block selected are turned on, the reference voltages generated by this block are applied to the comparators of the second comparator section 4 through lower-reference voltage lines L0 to L8. The voltage VL0 applied via the line L0 is lower than the voltage VL1 applied via the line L1, the voltage VL1 is lower than the voltage VL2 applied via the line L2, and so forth. That is, VL0&lt;VL1&lt;VL2 . . . &lt;VL8.
The input voltage Vin (i.e., the input analog data) is applied to the comparators CPM0 to CPM6 of the first comparator section 2, and also to the comparators CPL0 to CPL8 of the second comparator section 4. The output of the first comparator section 2 is supplied to the first encoder 3. The encoder 3 converts the output of the section 2 to upper three bits, which are input to the digital correction circuit 6. Meanwhile, the output of the second comparator section 4 is supplied to the second encoder 5. The encoder 5 converts the output of the section 4 to lower three bits, which are input to the digital correction circuit 6. The digital correction circuit 6 outputs 6-bit digital data.
How the series-parallel A/D converter operates when VRB&lt;VRT and the reference registers R0 to R63 divide the voltage (VRT-VRB), generating voltages Vr0 (=VRB) to Vr64 (=VRT), will be explained below.
Reference voltages Vr8, Vr18, Vr24, Vr32, Vr40, Vr48 and Vr56 which would be obtained by dividing the full-scale voltage (VRT-VRB) by eight (=2.sup.3) reference resistors and which define 3-bit resolution are input to the first comparator section 2. In the first comparator section 2, these seven reference voltages are compared with the input voltage Vin (i.e., the input analog data). The difference between each reference voltage and the input voltage Vin is thereby determined.
As shown in FIG. 1, eight groups S0 to S7 of switches are provided in the blocks BL0 to BL7, respectively. As seen from Table 1 presented below, the first comparator section 2 turns on the switches of the group used in the selected block, while maintaining the switches of any other group off.
TABLE 1 ______________________________________ Input voltage Vin States of the switches ______________________________________ Vr8 &gt; Vin Switches of group S0 are on Vr16 &gt; Vin &gt; Vr8 Switches of group S1 are on Vr24 &gt; Vin &gt; Vr16 Switches of group S2 are on . . . . . . Vin &gt; Vr56 Switches of group S7 are on ______________________________________
When the input voltage Vin is lower than Vr16 and higher than Vr8, for example, the first comparator section 2 turns on only the switches of the group S1 provided in the block BL1, while maintaining the switches of the groups S0 and S2 to S7 off.
Thereafter, nine reference voltages are compared with the input voltage Vin in the second comparator section 4. As shown in Table 2 below, the reference voltages are input to the second comparator section 4 through the lower-reference voltage lines L0 to L8. As mentioned above, the voltages VL0, VL1, VL2, . . . and VL8, which are applied via the lines L0 to L8, have the relationship of: VL0&lt;VL1&lt;VL2 . . . &lt;VL8.
TABLE 2 __________________________________________________________________________ Voltage lines Switches turned on L0 L1 L2 L3 L4 L5 L6 L7 L8 __________________________________________________________________________ S7 Vr56 Vr57 Vr58 Vr59 Vr60 Vr61 Vr62 Vr63 Vr64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S3 Vr24 Vr25 Vr26 Vr27 Vr28 Vr29 Vr30 Vr31 Vr32 S2 Vr16 Vr17 Vr18 Vr19 Vr20 Vr21 Vr22 Vr23 Vr24 S1 Vr8 Vr9 Vr10 Vr11 Vr12 Vr13 Vr14 Vr15 Vr16 S0 Vr0 Vr1 Vr2 Vr3 Vr4 Vr5 Vr6 Vr7 Vr8 __________________________________________________________________________
When the switches of the group S1 are on, that is, when the input voltage Vin is between Vr8 and Vr16, the reference voltages Vr8 to Vr16 are input to the second comparator section 4 through the lower-reference voltage lines L0 to L8.
The results of comparison performed in the first comparator section 2 are input to the first encoder 3. The encoder 3 converts the result of comparison to upper 3-bit digital data. On the other hand, the result of comparison performed in the second comparator section 4 is input to the second encoder 5. The encoder 5 converts the result of comparison to lower 3-bit digital data. The upper 3-bit digital data and the lower 3-bit digital data are input from the digital correction circuit 6. The circuit 6 eliminates the over-ranging of the lower 3-bit data and generates 6-bit digital data.
Assume that the switches of the group S0 are turned off and the switches of the group S1 are turned on in the reference voltage generator 1. In this case, the reference voltages applied through the lower-reference voltage lines L0 to L8 are changed, each by a value corresponding to eight reference resistors. Having the voltage generator 1 in which the reference voltages change so, the series-parallel A/D converter is disadvantageous in the following respects:
1. Since the halves of the input data (analog data) are independently converted to upper bits and lower bits, respectively, the reference voltages used in converting the second half of the input data to lower bits must be changed in accordance with the result of the comparison with the input voltage. To change the reference voltages, the A/D converter needs to have lower-reference voltage lines L0 to L8 and groups S0 to S7 of switches. When the switches of any group are turned on or off, the parasitic capacitances C0 to C8 of the lower-reference voltage lines L0 to L8 are charged or discharged, requiring some time (i.e., settling time). Consequently, the speed of converting the analog input data to digital data decreases.
2. If the input voltage Vin is nearly equal to any upper-reference voltage, the digital data the A/D converter outputs may be inaccurate. For instance, if the input voltage Vin is nearly equal to the upper-reference voltage Vr8, the switches of the group S0 or S1 are selected. If the switches of the group S0 are selected, the lower-reference voltage Vr8 is input to the comparator CPL8 via the lower-reference voltage line L8. If the switches of the group S1 are selected, the lower-reference voltage Vr8 is input to the comparator CPL0 through the lower-reference voltage line L0. Generally, if the voltage Vin is nearly equal to an upper-reference voltage Vri (i=8, 16, 32, 40, 48 or 56), the voltage Vri is input to one comparator or another, depending on which group of switches has been selected. The comparators differ in operating characteristic, inevitably because they have been made under different conditions. This is why the A/D converter may output inaccurate digital data if the input voltage Vin is nearly equal to any upper-reference voltage.